MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 49

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 29
Freescale Semiconductor
At recommended operating conditions OV
SD Card Output Hold
Note:
1
2
3
4
The symbols used for timing specifications herein follow the pattern of t
(reference)(state)
symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going
to high (H). Also t
to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is
based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
Measured at capacitive load of 40 pF.
For reference only, according to the SD card specifications.
Average, for reference only.
provides the eSDHC clock input timing diagram.
operational mode
External Clock
for inputs and t
Table 43. eSDHC AC Timing Specifications for High-Speed Mode (continued)
SFSKHOV
eSDHC
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Parameter
symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect
(first three letters of functional block)(reference)(state)(signal)(state)
Figure 29. eSDHC Clock Input Timing Diagram
DD
VM
= 3.3 V ± 165 mV.
VM = Midpoint Voltage (OVDD/2)
t
SHSCK
VM
Symbol
t
OH
VM
1
(first three letters of functional block)(signal)(state)
Enhanced Secure Digital Host Controller (eSDHC)
t
Min
2.5
SHSCK
t
for outputs. For example, t
SHSCKR
L
t
Max
SHSCKH
—
t
SHSCKF
Unit
ns
SFSIXKH
Notes
3
49