MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 47

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of
t
11.2.1.3
The following equation is the combined formula to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
11.2.2
Figure 28
11.2.2.1
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
Freescale Semiconductor
SFSCLKL
t
CLK_DELAY
t
t
CLK_DELAY
CLK_DELAY
= 20 ns:
provides the data and command input timing diagram.
Full-Speed Input Path (Read)
Full-Speed Write Combined Formula
Full-Speed Read Meeting Setup (Maximum Delay)
MPC8377E Pins
Output from the
MPC8377E Pin
SD CLK at the
+ t
t
SD Card Pins
CLK_DELAY
the Card Pin
Input at the
IH
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
SD CLK at
+ 5
< 15 + t
–
t
SFSKHOX
t
–
CLK_DELAY
t
CLK_DELAY
0 < 20 + t
DATA_DELAY
+ t
(MPC8377E Input Hold)
DATA_DELAY
< t
SFSCKL
+ t
DATA_DELAY
+ t
Figure 28. Full Speed Input Path
DATA_DELAY
IH
–
< t
t
+ t
SFSKHOX
SFSCK
DATA_DELAY
+ t
–
ODLY
< t
t
Driving
ODLY
SFSCKL
Edge
t
ODLY
< t
t
+ t
OH
t
t
SFSIXKH
–
SFSCK
SFSCK
SFSIVKH
t
SFSIVKH
+ t
t
CLK_DELAY
DATA_DELAY
(Clock Cycle)
+ t
Enhanced Secure Digital Host Controller (eSDHC)
CLK_DELAY
< t
–
t
SFSIVKH
t
SFSCK
DATA_DELAY
t
INT_CLK_DLY
–
t
ISU
–
Sampling
Edge
t
SFSKHOV
Eqn. 5
Eqn. 6
Eqn. 7
Eqn. 8
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