MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 54

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG
Figure 32
Figure 33
Figure 34
54
JTAG external clock to output high impedance:
Notes:
1
2
3
4
5
All outputs are measured from the midpoint voltage of the falling/rising edge of t
The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
The symbols used for timing specifications herein follow the pattern of t
for inputs and t
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. Also, t
data input signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
Non-JTAG signal input timing with respect to t
Non-JTAG signal output timing with respect to t
provides the AC test load for TDO and the boundary-scan outputs of the device.
provides the JTAG clock input timing diagram.
provides the TRST timing diagram.
Table 45. JTAG AC Timing Specifications (Independent of CLKIN)
External Clock
(first two letters of functional block)(reference)(state)(signal)(state)
TRST
Parameter
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
JTAG
Output
Figure 32. AC Test Load for the JTAG Interface
Figure 33. JTAG Clock Input Timing Diagram
Boundary-scan data
VM
t
JTKHKL
Figure 34. TRST Timing Diagram
VM
Z
VM = Midpoint Voltage (OVDD/2)
VM = Midpoint Voltage (OVDD/2)
0
TCLK
t
= 50 Ω
JTG
TCLK
TDO
.
VM
JTG
.
t
TRST
clock reference (K) going to the high (H) state. Note that, in general,
Symbol
t
t
JTKLOZ
JTKLDZ
JTDXKH
VM
2
for outputs. For example, t
symbolizes JTAG timing (JT) with respect to the time
(first two letters of functional block)(signal)(state) (reference)(state)
R
VM
L
= 50 Ω
Min
TCLK
t
2
2
JTGR
to the midpoint of the signal in question.
OVDD/2
Max
1
19
t
9
JTGF
(continued)
JTDVKH
Freescale Semiconductor
symbolizes JTAG
Unit
ns
Figure
JTG
clock
17).
Notes
5