MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 70

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial ATA (SATA)
Figure 45
16.2
This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA
interface.
16.2.1
Table 55
Gen1i or 1.5 Gbits/s transmission.
70
Tx differential output voltage
Tx differential pair impedance
Note:
1
SD_REF_CLK/ SD_REF_CLK
cycle to cycle Clock jitter (period
jitter)
SD_REF_CLK/ SD_REF_CLK total
reference clock jitter, phase jitter
(peak-peak)
Note:
1
2
3
Terminated by 50 Ω load.
Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system.
In a frequency band from 150 kHz to 15 MHz at BER of 10
Total peak to peak Deterministic Jitter "D
provides the DC differential transmitter output DC characteristics for the SATA interface at
Transmitter (Tx) Output Characteristics
shows the SATA reference clock timing waveform.
Parameter
Parameter
Gen1i/1.5G Transmitter Specifications
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Table 54. SATA Reference Clock Input Requirements (continued)
Ref_CLK
Table 55. Gen1i/1.5G Transmitter (Tx) DC Specifications
Figure 45. SATA Reference Clock Timing Waveform
Peak-to-peak jitter
Cycle-to-cycle at
at ref clock input
ref clock input
Condition
Z
V
SATA_TXDIFFIM
J
SATA_TXDIFF
" should be less than or equal to 50 ps.
Symbol
Symbol
t
t
CLK_CJ
CLK_PJ
-12
.
T
L
Min
400
85
Min
–50
—
Typical
T
500
100
H
Typical
—
—
Max
600
115
Max
100
+50
Freescale Semiconductor
mV
Units
Ω
Unit
p-p
ps
ps
Notes
Notes
—
2, 3
1
—