MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 87

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 71
Freescale Semiconductor
At recommended operating conditions with XV
Rising Edge Rate
Falling Edge Rate
Differential Input High Voltage
Differential Input Low Voltage
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Note:
1
2
3
4
Measurement taken from single ended waveform.
Measurement taken from differential waveform.
Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See
Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a
200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median
cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge
Rate of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference
should not exceed 20% of the slowest edge rate. See
SDn_REF_CLK
SDn_REF_CLK
VIH = +200 mV
VIL = –200 mV
describes some AC parameters common to PCI Express and SATA protocols.
Minus
SDn_REF_CLK
SDn_REF_CLK
V
0.0 V
CROSS MEDIAN
Figure 61. Single-Ended Measurement Points for Rise and Fall Time Matching
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Parameter
Figure 60. Differential Measurement Points for Rise and Fall Time
Rise Edge Rate
Table 71. SerDes Reference Clock Common AC Parameters
DD_SRDS
or XV
Figure
DD_SRDS
60.
Figure
V
V
Rise-Fall Matching
CROSS MEDIAN
CROSS MEDIAN
= 1.0 V ± 5%.
Rise Edge Rate
Fall Edge Rate
61.
Symbol
V
V
SDn_REF_CLK
SDn_REF_CLK
V
IH
IL
CROSS MEDIAN
+100 mV
–100 mV
Fall Edge Rate
Min
200
1.0
1.0
—
—
T
FALL
High-Speed Serial Interfaces (HSSI)
–200
Max
4.0
4.0
—
20
T
RISE
Unit
V/ns
V/ns
mV
mV
%
Notes
2, 3
2, 3
1, 4
2
2
87