MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 52

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG
11.3.2.1
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
This means that Data + Clock delay can be up to 11 ns for a 20 ns clock cycle:
11.3.2.2
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
This means that Data + Clock delay must be greater than ~6 ns for a 20 ns clock cycle:
11.3.2.3
The following equation is the combined formula to calculate the propagation delay range of the SD_CLK
and SD_DAT/CMD signals on the PCB.
12 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of
the MPC8377E.
52
0.5
t
t
10
6 < t
CLK_DELAY
CLK_DELAY
×
–
t
SHSCK
2.5 + (–1.5) < t
CLK_DELAY
High-Speed Read Meeting Setup (Maximum Delay)
High-Speed Read Meeting Hold (Minimum Delay)
High-Speed Read Combined Formula
0.5
0.5
×
×
–
t
t
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
t
+ t
+ t
SHSCK
OH
t
SHSCK
t
CLK_DELAY
CLK_DELAY
DATA_DELAY
DATA_DELAY
+ t
+ t
SHSIXKH
< t
–
DATA_DELAY
CLK_DELAY
t
OH
CLK_DELAY
+ t
+ t
+ t
< t
DATA_DELAY
DATA_DELAY
SHSIXKH
< 30
< 11
CLK_DELAY
+ t
+ t
–
DATA_DELAY
DATA_DELAY
–
14
t
INT_CLK_DLY
+ t
< 1.5
–
+ t
5
ODLY
DATA_DELAY
×
t
+ t
SHSCK
+ t
SHSIVKH
OH
< t
–
CLK_DELAY
–
t
< 1.5
t
SHSIXKH
ODLY
< 1.5
×
–
t
SHSCK
t
×
SHSIVKH
+ t
+ t
t
SHSCK
INT_CLK_DLY
DATA_DELAY
–
t
ODLY
–
t
Freescale Semiconductor
SHSIVKH
Eqn. 15
Eqn. 16
Eqn. 17
Eqn. 18
Eqn. 19