MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 50

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller (eSDHC)
11.3.1
Figure 30
11.3.1.1
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
Zero clock delay:
With clock delay:
This means that data delay should be equal or less than the clock delay in the ideal case where
t
50
SHSCLKL
t
t
DATA_DELAY
DATA_DELAY
= 10 ns:
provides the data and command output timing diagram.
High-Speed Output Path (Write)
MPC8377E Pins
Output from the
High-Speed Write Meeting Setup (Maximum Delay)
MPC8377E Pin
SD CLK at the
SD Card Pins
the Card Pin
Input at the
SD CLK at
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
–
–
t
t
t
t
CLK_DELAY
CLK_DELAY
SHSKHOV
Output Valid Time: t
Output Hold Time: t
DATA_DELAY
t
SHSKHOV
+ t
DATA_DELAY
Figure 30. High Speed Output Path
–
< 10
< 0
t
CLK_DELAY
+ t
t
SHSCK
SHSKHOV
SHSKHOX
–
Driving
DATA_DELAY
6
Edge
t
DATA_DELAY
–
4
(Clock Cycle)
+ t
< t
ISU
SHSCKL
< t
+ t
SHSCKL
ISU
–
t
t
< t
CLK_DELAY
ISU
t
ISU
SHSCKL
t
(6 ns)
+ t
SHSCKL
–
CLK_DELAY
t
SHSKHOV
Sampling
Edge
t
IH
(2 ns)
Freescale Semiconductor
Eqn. 10
Eqn. 11
Eqn. 12