MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 61

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.2
Table 51
15.3
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
15.4
Following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer please use the PCI Express
Base Specification, Rev. 1.0a.
Freescale Semiconductor
REFCLK cycle time
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles.
REFCLK phase jitter peak-to-peak. Deviation in edge
location with respect to mean edge location.
SD_REF_CLK/_B cycle to cycle clock jitter (period jitter)
SD_REF_CLK/_B phase jitter peak-to-peak. Deviation in
edge location with respect to mean edge location.
Note:
1
2
3
All options provide serial interface bit rate of 1.5 and 3.0 Gbps.
In a frequency band from 150 kHz to 15 MHz, at BER of 10
Total peak-to-peak Deterministic Jitter “J
lists the PCI Express SerDes clock AC requirements.
AC Requirements for PCI Express SerDes Clocks
Clocking Dependencies
Physical Layer Specifications
The voltage levels of the transmitter and the receiver depend on the SerDes
control registers which should be programmed at the recommended values
for PCI Express protocol (that is, L1_nV
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Parameter
Table 51. SD_REF_CLK and SD_REF_CLK AC Requirements
D
” should be less than or equal to 50 ps.
NOTE
-12
Symbol
t
t
.
REFCJ
REFPJ
t
t
t
CKPJ
CKCJ
REF
DD
= 1.0 V).
Min
–50
–50
—
—
—
Typical
10
—
—
—
—
Max
100
+50
100
+50
—
Unit
ns
ps
ps
ps
ps
PCI Express
Notes
2, 3
—
—
—
—
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