MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 83

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.2.3
The following list provides information about interfacing with other differential signaling levels.
Freescale Semiconductor
•
•
•
SDn_REF_CLK
SDn_REF_CLK
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are
HCSL (high-speed current steering logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC-coupled due to the limited common mode input range allowed
(100 mV to 400 mV) for DC-coupled connection.
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at
clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in
addition to AC-coupling.
Figure 54. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Interfacing With Other Differential Signaling Levels
SDn_REF_CLK
SDn_REF_CLK
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Figure 55. Single-Ended Reference Clock Input DC Requirements
200 mV < Input Amplitude or Differential Peak < 800 mV
400 mV < SDn_REF_CLK Input Amplitude < 800 mV
High-Speed Serial Interfaces (HSSI)
150
fdafdV
V
V
max
min
> V
< V
max
cm
cm
0 V
< V
– 400m V
+ 400 mV
cm
Vcm
+ 400 mV
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