MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 57

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 37
Figure 38
Freescale Semiconductor
All values refer to V
Data hold time
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including
hysteresis)
Noise margin at the HIGH level for each connected device (including
hysteresis)
Note:
1
2
3
The symbols used for timing specifications herein follow the pattern of t
for inputs and t
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
high (H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
MPC8377E provides a hold time of at least 300 ns for the SDA signal (referred to the V
undefined region of the falling edge of SCL.
The maximum t
SDA
SCL
provides the AC test load for the I
shows the AC timing diagram for the I
S
IH
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
(min) and V
t
I2CF
t
I2CL
t
I2SXKL
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
has only to be met if the device does not stretch the LOW period (t
Output
Parameter
IL
Table 47. I
(max) levels (see
I2SXKL
I2C
clock reference (K) going to the low (L) state or hold time. Also, t
Figure 38. I
CBUS compatible masters
t
I2DXKL
symbolizes I
2
C AC Electrical Specifications (continued)
Figure 37. I
Table
Z
t
I2DVKH
0
= 50 Ω
I
t
46).
2
2
I2CH
2
C bus devices
C.
C Bus AC Timing Diagram
2
C timing (I2) for the time that the data with respect to the start condition
t
2
I2SXKL
2
C bus.
C AC Test Load
Sr
for outputs. For example, t
Symbol
t
t
t
I2PVKH
I2KHDX
(first two letters of functional block)(signal)(state) (reference)(state)
I2DXKL
t
V
I2SVKH
V
NH
NL
t
I2KHKL
R
L
1
= 50 Ω
0.1 × OV
0.2 × OV
Min
0.6
1.3
IHmin
t
—
0
I2PVKH
I2C
OVDD/2
I2CL
DD
DD
clock reference (K) going to the
of the SCL signal) to bridge the
t
I2CR
) of the SCL signal.
I2DVKH
Max
0.9
—
—
—
—
—
I2PVKH
P
symbolizes I
t
I2CF
symbolizes I
Unit
μs
μs
μs
V
V
S
2
I2C
C timing
Notes
clock
2, 3
—
—
—
—
2
I
C
57
2
C