MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 103

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

State 0—The write cycle starts in S0. During S0, the QUICC places a valid address on A31–
A0 and valid function codes on FC3–FC0. The function codes select the address space for
the cycle. The QUICC drives R/W low for a write cycle. SIZ1 and SIZ0 become valid, indi-
cating the number of bytes to be transferred.
State 1—One-half clock later during S1, the QUICC asserts AS, indicating a valid address
on the address bus. During this state, any or all of the byte write enables (WE0, WE1, WE2,
and WE3) are asserted simultaneously with AS.
State 2—During S2, the QUICC places the data to be written onto D31–D0 and samples
DSACKx at the end of S2.
FC3–FC0
DSACK0
DSACK1
A31–A2
CLKO1
D31–D0
NOTE: WE3–WE0 is not shown.
R/W
SIZ1
SIZ0
AS
DS
A0
A1
S0
LONG WORD
S2
READ
Figure 4-20. Read-Write-Read Cycles—32-Bit Port
S4
Freescale Semiconductor, Inc.
For More Information On This Product,
S0
MC68360 USER’S MANUAL
Go to: www.freescale.com
S2
WRITE
S4
S0
S2
WRITE
S4
S0
S2
READ WITH WAIT STATES
Sw
Bus Operation
Sw
S4