MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 576

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
This command may be executed at any time, regardless of whether the Ethernet channel is
enabled.
If an address from the hash table must be deleted, the Ethernet channel should be disabled,
the hash table registers should be cleared, and the SET GROUP ADDRESS command must
be executed for the remaining desired addresses. This is required because the hash table
may have mapped multiple addresses to the same hash table bit.
7.10.23.11 ETHERNET ADDRESS RECOGNITION. The Ethernet controller can filter the
received frames based on different addressing types: physical (referred to as individual),
group (referred to as multicast), broadcast (an all-ones group address), and promiscuous.
The difference between an individual address and a group address is determined by the I/
G bit in the destination address field. A flowchart for address recognition on received frames
is shown in Figure 7-70.
In the physical type of address recognition, the Ethernet controller will compare the destina-
tion address field of the received frame with the physical address that the user programs in
the PADDR1. Alternatively, the user may perform address recognition on multiple individual
addresses using the IADDR1–4 hash table. See 7.10.23.12 Hash Table Algorithm for more
information.
In the group type of address recognition, the Ethernet controller will determine whether the
group address is a broadcast address. If broadcast addresses are enabled, then the frame
is accepted. If the group address is not a broadcast address, then the user may perform
address recognition on multiple group addresses using the GADDR1–4 hash table. See
7.10.23.12 Hash Table Algorithm for more information.
In the promiscuous mode, the Ethernet controller will receive all the incoming frames regard-
less of their address, unless the RRJCT pin is asserted.
If an external CAM is used for address recognition, then the user should select the promis-
cuous mode, and the frame can be rejected by assertion of the RRJCT pin during the recep-
tion of the frame. The on-chip address recognition functions may be used in addition to the
external CAM address recognition functions.
7-252
If the external CAM is used to store addresses that should be re-
jected, rather than accepted, then the use of the RRJCT pin by
the CAM should be logically inverted.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE