MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 282
MC68360CAI25L
Manufacturer Part Number
MC68360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
4.MC68360CAI25L.pdf
(24 pages)
Specifications of MC68360CAI25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Controller Family/series
68K
Core Size
32 Bit
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
Supply Voltage Range
3V To 3.6V, 4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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20 000
- MC68EN360VR25L PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68360AI25L PDF datasheet #3
- MC68360CAI25L PDF datasheet #4
- Current page: 282 of 962
- Download datasheet (4Mb)
System Integration Module (SIM60)
PIV7–PIV0—Periodic Interrupt Vector
6.9.3.7 PERIODIC INTERRUPT TIMER REGISTER (PITR). The PITR contains control for
prescaling the SWT and PIT as well as the count value for the PIT. This register can be read
or written at any time. Bits 15–10 are not implemented and always return zero when read.
A write does not affect these bits.
SWP—Software Watchdog Prescaler Control
PTP—Periodic Timer Prescaler Control
PITR7–PITR0—Periodic Interrupt Timer Register
6-38
RESET:
15
These bits contain the value of the vector generated during an interrupt acknowledge cy-
cle in response to an interrupt from the PIT. When the SIM60 responds to the interrupt
acknowledge cycle, the periodic interrupt vector from the PICR is placed on the bus. This
vector number is multiplied by 4 to form the vector offset, which is added to the VBR in
the CPU32+ to obtain the address of the vector.
This bit controls the SWT clock source as shown in 6.9.3.5 System Protection Control
Register (SYPCR). The SWP reset value is the inverse of the MODCK1 pin state on the
rising edge of reset.
This bit contains the prescaler control for the PIT. The PTP reset value is the inverse of
the MODCK1 pin state on the rising edge of reset.
These bits contain the remaining bits of the PITR count value for the PIT. A zero value
turns off the PIT. These bits may be written at any time to modify the PIT count value.
0
0
0 = SWT clock is not prescaled.
1 = SWT clock is prescaled by a value of 512.
0 = PIT clock is not prescaled.
1 = PIT clock is prescaled by a value of 512.
14
0
0
13
0
0
Table 6-6. Periodic Interrupt Request Level Encoding
PIRQL2
12
0
0
0
0
0
0
1
1
1
1
Freescale Semiconductor, Inc.
11
0
0
For More Information On This Product,
PIRQL1
10
0
0
0
0
1
1
0
0
1
1
MC68360 USER’S MANUAL
MODCK
Go to: www.freescale.com
SWP
1
9
PIRQL0
MODCK
PTP
1
8
0
1
0
1
0
1
0
1
PITR7
7
0
PIT Disabled
Interrupt Request Level 1
Interrupt Request Level 2
Interrupt Request Level 3
Interrupt Request Level 4
Interrupt Request Level 5
Interrupt Request Level 6
Interrupt Request Level 7
PITR6
Interrupt Request Level
6
0
PITR5
5
0
PITR4
4
0
PITR3
3
0
PITR2
2
0
SUPERVISOR ONLY
PITR1
1
0
PITR0
0
0
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