MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 134

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
The QUICC has another mechanism to assign priorities to the bus masters. A new pin called
bus clear in (BCLRI) is defined. BCLRI indicates to the QUICC that a request is being made
for the QUICC to release the system bus. The QUICC will then clear all internal bus masters
with an arbitration ID smaller than the programmed value of the bus clear in ID (BCLRIID)
in the MCR.
Slave (disable CPU32+) mode bus arbitration has fewer arbitration modes than exist in a
normal mode, since in slave mode, the SHEN1-SHEN0 bits are forced to be "00":
See Figure 4-40 for the slave mode bus arbitration timing diagram.
4-58
• In synchronous mode (ASTM bit in the MCR is set), BG and BGACK have synchronous
• In asynchronous mode, the minimum time for BGACK assertion after BG is asserted
• The QUICC will not request the external bus (assert BR) when one of its internal mas-
timing, and the minimal delay between the assertion of BG (negation of BGACK) and
the assertion of BGACK is one clock.
(BGACK is negated) depends on internal synchronization.
ters is making an internal access. The QUICC will request the external bus only when
one of its internal masters is beginning an external access. In this case, the arbitration
overhead (external bus idle time is minimal).
DSACK1-DSACK0
NOTES:
1. Synchronous arbitration with SHEN1–SHEN0 = 00.
2. Minimum bus idle time.
BR (OUT)
(IN/OUT)
BGACK
A31–A0
D31–D0
BG (IN)
CLKO1
Figure 4-40. Slave Mode Bus Arbitration Timing Diagram
R/W
AS
DS
Freescale Semiconductor, Inc.
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S0
S1
S2
S3
S4
S5