MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 458

IC MPU QUICC 25MHZ 240-FQFP

MC68360CAI25L

Manufacturer Part Number
MC68360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor

Specifications of MC68360CAI25L

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Controller Family/series
68K
Core Size
32 Bit
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
Supply Voltage Range
3V To 3.6V, 4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

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Serial Communication Controllers (SCCs)
If the CD pin is programmed to envelope the data, the CD pin must remain asserted during
frame transmission, or a CD lost error occurs. The negation of the CD pin terminates recep-
tion. If the CDS bit in the GSMR is zero, the CD pin must be sampled by the SCC before a
CD lost is recognized. Otherwise, the negation of CD immediately causes the CD lost con-
dition.
7.10.11.2 ASYNCHRONOUS PROTOCOLS. The RTS pin is asserted when the SCC data
is loaded into the transmit FIFO and a falling transmit clock occurs. The CD and CTS pins
may be used to control reception and transmission in the same manner as the synchronous
protocols. The first bit of data transmission in an asynchronous protocol is the start bit of the
first character. In addition, the UART protocol has an option for CTS flow control as
described in 7.10.16 UART Controller.
7-134
(INPUT)
NOTES:
(INPUT)
NOTES:
(INPUT)
(INPUT)
RCLK
1. CDS = 0 in GSMR; CDP = 0.
2. If CD is negated prior to the last bit of the receive frame, CD LOST is signaled in the frame BD.
3. If CDP = 1, CD LOST cannot occur, and CD negation has no effect on reception.
RXD
RCLK
3. If CDP = 1, CD lost cannot occur, and CD negation has no effect on reception.
CD
1. CDS = 1 in GSMR; CDP = 0.
2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the frame BD.
RXD
CD
Figure 7-42. Using CD to Control Reception of Synchronous Protocols
If the CDS bit in GSMR is set, all CD transitions must occur while
the receive clock is low.
Freescale Semiconductor, Inc.
CD ASSERTION IMMEDIATELY
GATES RECEPTION
FIRST BIT OF DATA IN FRAME
FIRST BIT OF FRAME DATA
For More Information On This Product,
CD SAMPLED LOW HERE
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
CD NEGATION IMMEDIATELY
LAST BIT OF FRAME DATA
LAST BIT OF FRAME DATA
CD SAMPLED HIGH HERE
HALTS RECEPTION

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