MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 517
MC68360CAI25L
Manufacturer Part Number
MC68360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
4.MC68360CAI25L.pdf
(24 pages)
Specifications of MC68360CAI25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Controller Family/series
68K
Core Size
32 Bit
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
Supply Voltage Range
3V To 3.6V, 4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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- MC68EN360VR25L PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68360AI25L PDF datasheet #3
- MC68360CAI25L PDF datasheet #4
- Current page: 517 of 962
- Download datasheet (4Mb)
To ensure that all stations gain an equal share of the bus, a priority mechanism is also imple-
mented in HDLC bus. Once an HDLC bus node has completed the transmission of a frame,
it waits for 10 consecutive one bits, rather than just 8, before beginning the next transmis-
sion. In this way, all nodes desiring to transmit will obtain the bus, before a node transmits
twice. Once a node detects that 10 consecutive ones have occurred on the bus, it may
attempt transmission and can reinstate its original priority of waiting for 8 ones.
7.10.18.2.2 More Performance. Since HDLC bus is used in a wired-OR configuration, the
limit of HDLC bus operation is determined by the rise time of the one bit.
Figure 7-57 shows a method to increase performance. The user supplies a clock that is high
for a shorter duration than it is low, which allows more rise time in the case of a one bit.
(OUTPUT)
(INPUT)
TCLK
TXD
CTS
(OUTPUT)
(INPUT)
TCLK
TXD
CTS
Figure 7-56. HDLC Bus Collision Detection
Figure 7-57. Non-Symmetrical Duty Cycle
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)
CTS SAMPLED AT HALFWAY POINT.
COLLISION DETECTED WHEN
TXD = 1, BUT CTS = 0.
CTS sampled at three quarter point.
Collision detected when
TXD = 1, but CTS = 0.
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