MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 289

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RW1–RW0—Read/Write Selection
SIZM—Size Mask
SIZ1–SIZ10—Size Bits
Assert a breakpoint match on read cycles only, write cycles only, or on both.
This bit determines whether the breakpoint logic will use the SIZ bits to determine whether
a breakpoint match has occurred.
The breakpoint logic can cause a breakpoint match for accesses that correspond to the
size of the access. Set the SIZM bit to disable this feature.
00 = Assert breakpoint on read cycles.
01 = Assert breakpoint on write cycles.
10 = Assert breakpoint on read or write cycles.
11 = Reserved.
0 = Compare the size lines as programmed in the SIZ bits to determine whether a
1 = Mask the size lines. The size of the access is not used in determining whether a
breakpoint match has occurred.
breakpoint match has occurred. The breakpoint logic will assert the break signal
when the address and size overlaps the programmable value. For example if the
programmable address is xxx2, the breakpoint line for the low word will be asserted
when the access address is xxx2 with a word size or when the address is xxx0 with
a long-word size.
This mode is used in QUICC slave operation to assert either the
BKPTO line for the external CPU or the internal IMB BKPT line
for an internal-to-internal IDMA/SDMA access. When the exter-
nal bus is used, the breakpoint line will be asserted as if the
SIZM bit is set.
In the case of an external MC68040 burst, only the first address
of the burst is checked.
When the QUICC is in master mode this bit should be zero to
prevent external breakpoint from being ignored.
This mode would normally be used to break on an access to a
location that contains data.
This mode would normally be used to break on an instruction
fetch.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
NOTE
NOTE
System Integration Module (SIM60)