MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 122

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
4.5.3 Halt Operation
When HALT is asserted and BERR is not asserted, the QUICC halts external bus activity at
the next bus cycle boundary (see Figure 4-33). HALT by itself does not terminate a bus
cycle. HALT affects external bus cycles only; thus, a program that does not require use of
the external bus may continue executing until it requires use of the external bus.
Negating and reasserting HALT in accordance with the correct timing requirements provides
a single step (bus cycle to bus cycle) operation. The single-cycle mode allows the user to
proceed through (and debug) external QUICC operations, one bus cycle at a time. Since the
occurrence of a bus error while HALT is asserted causes a retry operation, the user must
anticipate retry cycles while debugging in the single-cycle mode. The single-step operation
and the software trace capability allow the system debugger to trace single bus cycles, sin-
gle instructions, or changes in program flow.
4-46
tire word access will be retried. This is true even if the relinquish
and retry was asserted on the second access and the first 8-bit
access was completed normally.
FC3–FC0
D31–D10
DSACKx
A31–A0
CLKO1
BERR
HALT
R/W
AS
DS
S0
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 4-32. Late Retry Sequence
S2
WRITE
CYCLE
MC68360 USER’S MANUAL
Go to: www.freescale.com
S4
HALT
S0
S2
RERUN
WRITE
S4