MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 239
![IC MPU QUICC 25MHZ 240-FQFP](/photos/39/60/396094/4532975_sml.jpg)
MC68360CAI25L
Manufacturer Part Number
MC68360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
4.MC68360CAI25L.pdf
(24 pages)
Specifications of MC68360CAI25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Controller Family/series
68K
Core Size
32 Bit
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
Supply Voltage Range
3V To 3.6V, 4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360CAI25L
Manufacturer:
SAMTEC
Quantity:
1 000
Company:
Part Number:
MC68360CAI25L
Manufacturer:
FREESCAL
Quantity:
717
Company:
Part Number:
MC68360CAI25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68360CAI25L
Manufacturer:
FREESCALE
Quantity:
20 000
- MC68EN360VR25L PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68360AI25L PDF datasheet #3
- MC68360CAI25L PDF datasheet #4
- Current page: 239 of 962
- Download datasheet (4Mb)
ber of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are
included in the total clock cycle number. All timing data assumes two-clock reads and writes.
5.7.2.10 BIT MANIPULATION INSTRUCTIONS. The bit manipulation instruction table indi-
cates the number of clock periods needed for the processor to perform the specified opera-
tion on the given addressing mode. The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle
number. All timing data assumes two-clock reads and writes.
LSd
LSd
LSd
ASd
ASd
ASd
ROd
ROd
ROd
ROXd
ROXd
ROXd
d = Direction (left or right)
NOTES:
1. Head and cycle times can be derived from the following table or calculated as follows:
2. Head and cycle times are calculated as follows: (count
3. Head and cycle times are calculated as follows: (count
4. Timing is calculated with the CPU32+ in 16-bit mode.
Clocks
Max (3
10
12
14
16
18
20
22
6
8
(n/4)
15
23
31
39
47
55
63
0
7
Dn, Dm
#, Dm
Dn, Dm
#, Dm
Dn, Dm
#, Dm
Dn, Dm
#, Dm
FEA
FEA
FEA
FEA
mod(n,4)
10
18
26
34
42
50
58
1
Instruction
Freescale Semiconductor, Inc.
For More Information On This Product,
mod (((n/4)
11
19
27
35
43
51
59
2
MC68360 USER’S MANUAL
Go to: www.freescale.com
13
21
29
37
45
53
61
3
mod (n,4)
Shift Counts
14
22
30
38
46
54
62
4
1,2), 6)
63): max (3
8): max (2
16
24
32
40
48
56
5
Head
4
0
4
0
4
0
0
2
2
2
2
2
n
17
25
33
41
49
57
6
n
mod (n,2), 6).
mod (n
Tail
0
0
2
0
0
2
0
0
2
0
0
2
20
28
36
44
52
60
8
1,2), 6).
6(0/1/0)
6(0/1/1)
6(0/1/0)
6(0/1/1)
6(0/1/0)
6(0/1/1)
6(0/1/1)
Cycles
(0/1/0)
(0/1/0)
(0/1/0)
(0/1/0)
(0/1/0)
9
Note
—
—
—
—
—
—
—
12
1
1
1
2
3
CPU32+
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