MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 399

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.8.4.6 SI RAM PROGRAMMING EXAMPLE. This example shows how to program the
RAM to support the 10-bit IDL bus (see Figure 7-33 for the 10-bit IDL bus format).
In this example, the TSA supports the B1 channel with SCC2, the D channel with SCC1, the
first 4 bits of the B2 channel with an external device (using a strobe to enable the external
device), and the last 4 bits of B2 with SCC4. Additionally, the TSA will mark the D channel
with another strobe signal.
First, divide the frame from the start (i.e., the sync) to the end of the frame according to the
support that is required:
Each of these six divisions can be supported by just one SI RAM entry. Thus, a total of only
six entries is needed in the SI RAM:
7.8.4.7 SI RAM DYNAMIC CHANGES. The SI RAM, described in 7.8.4.5 Programming SI
RAM Entries, has four operating modes:
1. 8 bits (B1)—SCC2
2. 1 bit (D)—SCC1 + strobe1
3. 1 bit—no support
4. 4 bits (B2)—strobe2
5. 4 bits (B2)—SCC4
6. 1 bit (D)—SCC1 + strobe1
1. One TDM with a static routing definition. SI RAM divided into two parts (Rx and Tx).
2. One TDM allowing dynamic changes. SI RAM divided into four parts.
3. Two TDMs with static routing definition. SI RAM divided into four parts.
4. Two TDMs allowing dynamic changes. SI RAM divided into eight parts.
Since IDL requires the same routing for both receive and trans-
mit, an exact duplicate of the above entries should be written to
both the receive and transmit sections of the SI RAM. Then the
CRTx bit in the SIMODE register can be used to instruct the SI
RAM to use the same clock and sync to simultaneously control
both sets of SI RAM entries.
Entry
No.
1
2
3
4
5
6
SWTR
0
0
0
0
0
0
Freescale Semiconductor, Inc.
For More Information On This Product,
SSEL
0000
0001
0000
0010
0000
0001
MC68360 USER’S MANUAL
Go to: www.freescale.com
CSEL
010
001
000
000
100
001
0000
0000
0000
0011
0011
0000
CNT
NOTE
RAM WORD
BYT
1
0
0
0
0
0
Serial Interface with Time Slot Assigner
LST
0
0
0
0
0
1
1 Bit SCC1 Strobe1
1 Bit SCC1 Strobe1
1 Bit No Support
4 Bits Strobe2
description
8 Bits SCC2
4 Bits SCC4