MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 615
MC68360CAI25L
Manufacturer Part Number
MC68360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
4.MC68360CAI25L.pdf
(24 pages)
Specifications of MC68360CAI25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Controller Family/series
68K
Core Size
32 Bit
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
Supply Voltage Range
3V To 3.6V, 4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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- MC68EN360VR25L PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68360AI25L PDF datasheet #3
- MC68360CAI25L PDF datasheet #4
- Current page: 615 of 962
- Download datasheet (4Mb)
7.11.9 SMC Interrupt Handling
The following list describes what would normally occur within an interrupt handler for the
SMC:
7.11.10 SMC as a Transparent Controller
The following paragraphs describe using the SMC as a transparent controller.
7.11.10.1 SMC TRANSPARENT CONTROLLER KEY FEATURES. The SMC transparent
controller contains the following key features:
14. Write $FF to the SMCE to clear any previous events.
15. Write $17 to the SMCM to enable all possible SMC interrupts.
16. Write $00000010 to the CIMR to allow SMC1 to generate a system interrupt. (The
17. Write $4820 to SMCMR to configure normal operation (not loopback), 8-bit
18. Write $4823 to SMCMR to enable the SMC transmitter and receiver. This
1. Once an interrupt occurs, read the SMCE to see which sources have caused inter-
2. Process the Tx BD to reuse it if the TX bit was set in SMCE. Extract data from the Rx
3. Clear the SMC1 bit in the CISR.
4. Execute the RTE instruction.
• Flexible Data Buffers
• May Be Used To Connect to a TDM Bus using the TSA in the SI
• May Transmit and Receive Transparently on Its Own Set of Pins using a Sync Pin To
• Programmable Character Length (4–16)
• Reverse Data Mode
Synchronize the Beginning of Transmission and Reception to an External Event
and contains five 8-bit characters. Write $B000 to Tx_BD_Status. Write $0005 to
Tx_BD_Length. Write $00002000 to Tx_BD_Pointer.
CICR should also be initialized.)
characters, no parity, 1 stop bit. Notice that the transmitter and receiver have
not been enabled yet.
additional write ensures that the TEN and REN bits will be enabled last.
rupts. The SMCE bits would normally be cleared at this time.
BD if the RX bit was set in SMCE. To transmit another buffer, simply set the Tx BD R-
bit.
After 5 bytes have been transmitted, the Tx BD is closed. Addi-
tionally, the receive buffer is closed after 16 bytes have been re-
ceived. Any additional receive data beyond 16 bytes will cause
a busy (out-of-buffers) condition since only one Rx BD was pre-
pared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Serial Management Controllers (SMCs)
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