MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 202

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
By contrast, an integrated debugger supports use of a bus state analyzer (BSA) for in-circuit
emulation. The processor remains in the target system (see Figure 5-19), and the interface
is simplified. The BSA monitors target processor operation and the on-chip debugger con-
trols the operating environment. Emulation is much closer to target hardware; thus, many
interfacing problems (i.e., limitations on high-frequency operation, AC and DC parametric
mismatches, and restrictions on cable length) are minimized.
5.6.1.2 DETERMINISTIC OPCODE TRACKING OVERVIEW. CPU32+ function code out-
puts are augmented by three supplementary signals that monitor the instruction pipeline.
The IFETCH output signal identifies bus cycles in which data is loaded into the pipeline and
signals pipeline flushes. The IPIPE1, IPIPE0 output signals indicate when each mid-instruc-
tion pipeline advance occurs and when instruction execution begins. These signals allow a
BSA to synchronize with instruction stream activity. Refer to 5.6.3 Deterministic Opcode
Tracking for complete information.
5.6.1.3 ON-CHIP HARDWARE BREAKPOINT OVERVIEW. An external breakpoint input
and an on-chip hardware breakpoint capability permit breakpoint trap on any memory
access. Off-chip address comparators will not detect breakpoints on internal accesses
unless show cycles are enabled. Breakpoints on prefetched instructions, which are flushed
from the pipeline before execution, are not acknowledged, but operand breakpoints are
always acknowledged. Acknowledged breakpoints can initiate either exception processing
or BDM. See 5.5.2.6 Hardware Breakpoints for more information.
5.6.2 Background Debug Mode
BDM is an alternate CPU32+ operating mode. During BDM, normal instruction execution is
suspended, and special microcode performs debugging functions under external control.
Figure 5-20 is a BDM block diagram.
BDM can be initiated in several ways—by externally generated breakpoints, by internal
peripheral breakpoints, by the background instruction (BGND), or by catastrophic exception
conditions. While in BDM, the CPU32+ ceases to fetch instructions via the parallel bus and
communicates with the development system via a dedicated, high-speed, SPI-type serial
command interface.
5.6.2.1 ENABLING BDM. Accidentally entering BDM in a nondevelopment environment
could lock up the CPU32+ since the serial command interface would probably not be avail-
able. For this reason, BDM is enabled during reset via the BKPT signal.
5-60
TARGET
SYSTEM
TARGET
MCU
Figure 5-19. Bus State Analyzer Configuration
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
BUS STATE
ANALYZER