MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 792

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Applications
9.7.4 Test Pattern Generation
The easiest way to generate the test pattern is to use the QUICC CPU32+ to transfer the
test pattern over its I/O pins using a bit-banging technique.
The test pattern output data is written to the I/O ports, and therefore to the pins, by writing
to the digital output ports (MTCK, MTMS, and MTDI); the result is read back by simply read-
ing the MTDO pin. A data area is created in memory to hold the test pattern. The CPU32+
compares the result on the MTDO pin to the respective expected result in memory.
Figure 9-26 shows an example of the pattern that would be stored in the memory array. The
three leftmost columns are output signals written to the I/O port, and the right column is the
result expected to be read back. Since the clock signal is part of the pattern and not sepa-
rately generated, both clock phases are represented, and thus two entries comprise each
TCK clock cycle.
9-72
TDO
TMS
TCK
TDI
MUX:
IF MM = 1 THEN B
IF MM = 0 THEN A
FROM LAST DEVICE IN SCAN LOOP
A
B
MUX
EN
OUT
Figure 9-25. Signal Routing for Test Bus Master
TO FIRST DEVICE IN SCAN LOOP
Freescale Semiconductor, Inc.
For More Information On This Product,
A
B
MUX
EN
OUT
MC68360 USER’S MANUAL
Go to: www.freescale.com
A
B
MUX
EN
OUT
EN
IN TEST MASTER MODE
I/O FUNCTIONS IF NOT
LATCH
MTDI
MTMS
MTCK
MTDO
MM
QUICC WITHOUT
TAP IN USE