MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 748

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Applications
The HDLC mode register is implemented using the GSMR and the PSMR. One GSMR and
one PSMR exist for each SCC. The definition of the PSMR differs based on the protocol
used.
The BISYNC mode register is implemented using the GSMR and the PSMR. One GSMR
and one PSMR exist for each SCC. The definition of the PSMR differs based on the protocol
used.
The DDCMP mode register is a microcode RAM product on the QUICC. The port of DDCMP
from the MC68302 is not discussed in this section.
The V.110 mode register is not supported on the QUICC.
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The TPM bits remain the same and are located in the PSMR.
The ENC bit becomes the TENC and RENC bits in the GSMR. Note that the QUICC con-
tains many more data encoding options.
The FLG bit becomes the RTSM bit in the GSMR.
The RTE bit is located in the PSMR.
The FSE bit is located in the PSMR.
The C32 bit becomes the two CRC bits in the PSMR. If C32 = 0, then initialize CRC to 00.
If C32 = 1, then initialize CRC to 10.
The NOF bits are located in the PSMR.
The ENC bit becomes the TENC and RENC bits in the GSMR. Note that the QUICC con-
tains many more data encoding options.
The SYNF bit becomes the RTSM bit in the GSMR.
The RBCS bit is located in the PSMR.
The RTR bit is located in the PSMR.
The BCS bit becomes the two CRC bits in the PSMR. If BCS = 0, initialize CRC to 11. If
BCS = 1, initialize CRC to 01.
The REVD bit becomes the RVD bit in the PSMR. Note that the RVD bit in the PSMR is
not the same as the REVD bit in the GSMR.
The NTSYN bit should not have been set in BISYNC mode, and therefore is not ported.
If the EXSYN bit was set, the CDP and CTSP bit in the GSMR should be set for compat-
ibility. The user may also wish to leave the CDS and CTSS bits cleared in the GSMR.
The PM bit becomes the TPM and RPM bits in the PSMR. Note that more parity options
are now available.
The SYNL bits in the GSMR were added to offer more synchro-
nization options than are available on the MC68302.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE