MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 664
![IC MPU QUICC 25MHZ 240-FQFP](/photos/39/60/396094/4532975_sml.jpg)
MC68360CAI25L
Manufacturer Part Number
MC68360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
4.MC68360CAI25L.pdf
(24 pages)
Specifications of MC68360CAI25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Controller Family/series
68K
Core Size
32 Bit
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
Supply Voltage Range
3V To 3.6V, 4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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SAMTEC
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MC68360CAI25L
Manufacturer:
FREESCAL
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MC68360CAI25L
Manufacturer:
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Quantity:
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Part Number:
MC68360CAI25L
Manufacturer:
FREESCALE
Quantity:
20 000
- MC68EN360VR25L PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68360AI25L PDF datasheet #3
- MC68360CAI25L PDF datasheet #4
- Current page: 664 of 962
- Download datasheet (4Mb)
Parallel Interface Port (PIP)
TMOD—Timing Mode (Centronics Receiver)
MODL—Mode Low
MODH—Mode High
HSC—Host Control
7-340
When T/R = 1 (PIP is a transmitter), the definition is as follows:
These bits are only valid when T/R is set to receive and MODH is set to pulsed handshake
mode. Otherwise they are ignored.
These bits determine the mode of the PIP’s lower 8 pins (PB7–PB0).
These bits determine the mode of the PIP’s upper 10 pins (PB17–PB8). MODH may be
changed when the RISC processor is not currently receiving or transmitting data.
0 = Ignore the BUSY signal input on PB0 for the transmitter.
1 = Assertion of STB is conditioned by BUSY is negation. STB will not be asserted until
00 = Centronics receiver timing mode 0 (BUSY is negated before ACK is asserted).
01 = Centronics receiver timing mode 1 (BUSY is negated after ACK assertion but be-
10 = Centronics receiver timing mode 2 (BUSY is negated after ACK negation).
11 = Centronics receiver timing mode 3 (BUSY is negated by host software).
00 = Port B general-purpose I/O mode (under host control).
01 = Transparent handshake mode (under RISC or host control).
1x = Mode of operation is controlled by MODH.
00 = Port B general-purpose I/O (under host control).
01 = Transparent handshake mode (under RISC or host control).
10 = Interlocked handshake mode (under RISC or host control).
11 = Pulsed handshake mode (under RISC or host control).
0 = The PIP data transfers are controlled by the RISC in the CPM, using the PIP pa-
1 = The PIP data transfers are controlled by the host software (i.e., CPU32+ or other
the BUSY signal, input on PB0, is negated. EBSY will only take effect if bit 0 of PB-
PAR is 0 to configure this pin to belong to the PIP and bit 0 of PBDIR is 0 to make
this pin an input.
rameter RAM, BDs, and SDMA channels.
external processor in the system).
fore ACK negation).
The programming of MODL has no effect on the BUSY pin if
EBSY is set.
The BUSY pin (PB0) is not affected by MODL programming if
EBSY is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE
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