MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 209

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

the bus is not being monitored. Each method requires a slightly different serial logic design
to avoid spurious serial clocks.
Figure 5-24 represents the timing required for asserting BKPT during a single bus cycle.
Figure 5-25 depicts the timing of the BKPT/FREEZE method. In both cases, the serial clock
is left high after the final shift of each transfer. This technique eliminates the possibility of
accidentally tagging the prefetch initiated at the conclusion of a BDM session. As mentioned
previously, all timing within the CPU is derived from the rising edge of the clock; the falling
edge is effectively ignored.
Figure 5-26 represents a sample circuit providing for both BKPT assertion methods. As the
name implies, FORCE_BGND is used to force a transition into BDM by the assertion of
BKPT. FORCE_BGND can be a short pulse or can remain asserted until FREEZE is
asserted. Once asserted, the set-reset latch holds BKPT low until the first SHIFT_CLK is
applied.
FORCE_BGND
FORCE_BGND
BKPT_TAG
BKPT_TAG
SHIFT_CLK
SHIFT_CLK
FREEZE
FREEZE
BKPT
BKPT
Figure 5-24. BKPT Timing for Single Bus Cycle
FORCE_BGND
SHIFT_CLK
Figure 5-25. BKPT Timing for Forcing BDM
BKPT_TAG
Figure 5-26. BKPT/DSCLK Logic Diagram
Freescale Semiconductor, Inc.
RESET
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
S2
R
S1
Q
Q
BKPT/DSCLK
CPU32+