dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 103

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

the user condition code register (CCR) occupying the low-order eight bits. The SR may
be accessed as a word operand.
The MR and CCR may be accessed individually as word operands (see Figure 6-6(b)).
The LC, LA, system stack high (SSH), and system stack low (SSL) registers are 16 bits
wide and may be accessed as word operands (see Figure 6-6(a)). When used as a source
operand, these registers occupy the low-order portion of the 24-bit word; the high-order
portion is zero. When used as a destination operand, they receive the low-order portion
of the 24-bit word; the high-order portion is not used. The system stack pointer (SP) is a
6-bit register that may be accessed as a word operand
The PC, a special 16-bit-wide program control register, is always referenced implicitly as
a short-word operand.
6.3.3 Data Organization in Memory
The 24-bit program memory can store both 24-bit instruction words and instruction exten-
sion words. The 32-bit system stack (SS) can store the concatenated PC and SR registers
(PC:SR) for subroutine calls, interrupts, and program looping. The SS also supports the
concatenated LA and LC registers (LA:LC) for program looping. The 24-bit-wide X and Y
memories can store word, short-word, and byte operands. Short-word and byte operands,
which usually occupy the low-order portion of the X or Y memory word, are either zero
extended or sign extended on the XDB or YDB.
The symbols used to abbreviate the various operands and operations in each instruction
and their respective meanings are shown in the following list:
Data ALU
MOTOROLA
*Data Move Operations: when specified as a source operand, shifting and limiting
are performed. When specified as a destination operand, sign extension and zero
filling are performed.
Xn
Yn
An
Bn
X
Y
A
B
AB
Input Registers X1, X0 (24 Bits)
Input Registers Y1, Y0 (24 Bits)
Accumulator Registers A2 (8 Bits), A1, A0 (24 Bits)
Accumulator Registers B2 (8 Bits), B1, B0 (24 Bits)
Input Register X (X1:X0, 48 Bits)
Input Register Y (Y1:Y0, 48 Bits)
Accumulator A (A2:A1:A0, 56 Bits)
Accumulator B (B2:B1:B0, 56 Bits)
Accumulators A and B (A1:B1, 48 Bits)
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