dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 157

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

mented to one (see Figure 7-13). During the execution of n2 in Figure 7-13, no interrupts
will be serviced. When LC finally decrements to one, the fetches are reinitiated, and
pending interrupts can be serviced.
Sequential REP packages will cause pending interrupts to be rejected until the sequence
of REP packages ends. REP packages are not interruptible because the instruction
being repeated is not refetched. While that instruction is repeating, no instructions are
fetched or decoded, and an interrupt can not be inserted. For example, in Figure 7-14, if
n1, n3, and n5 are all REP instructions, no interrupts will be serviced until the last REP
instruction (n5 and its repeated instruction, n6) completes execution.
7.4
The processor enters the reset processing state when a hardware reset occurs and the
external RESET pin is asserted. The reset state:
When the processor deasserts the reset state:
MOTOROLA
RESET PROCESSING STATE
1. resets internal peripheral devices;
2. sets the modifier registers to $FFFF;
3. clears the interrupt priority register;
4. sets the BCR to $FFFF, thereby inserting 15 wait states in all external memory
5. clears the stack pointer;
6. clears the scaling mode, trace mode, loop flag, double precision multiply
7. clears the data ROM enable bit, the stop delay bit, and the internal Y memory
8. the DSP remains in the reset state until the RESET pin is deasserted.
9. it loads the chip operating mode bits of the OMR from the external mode select
10. begins program execution at program memory address defined by the state of
accesses;
mode, and condition code bits of the SR, and sets the interrupt mask bits of
the SR;
disable bit, and
pins (MODA, MODB, MODC), and
bits MODA, MODB, and MODC in the OMR. The first instruction must be
fetched and then decoded before executing. Therefore, the first instruction
execution is two instruction cycles after the first instruction fetch.
Freescale Semiconductor, Inc.
For More Information On This Product,
RESET PROCESSING STATE
PROCESSING STATES
Go to: www.freescale.com
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