dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 186

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

CLVCC
CLGND GND for the CKOUT output. The pin should be provided with an extremely low
PCAP
CKOUT This output pin provides a 50% duty cycle output clock synchronized to the
CKP
PINIT
PLOCK The PLOCK output originates from the Phase Detector. The chip asserts
9 - 10
VCC for the CKOUT output. The voltage should be well regulated and the pin
should be provided with an extremely low impedance path to the VCC power
rail. CLVCC should be bypassed to CLGND by a 0.1 F capacitor located as
close as possible to the chip package.
impedance path to ground. CLVCC should be bypassed to CLGND by a 0.1 F
capacitor located as close as possible to the chip package.
Off-chip capacitor for the PLL filter. One terminal of the capacitor is connected
to PCAP while the other terminal is connected to PVCC. The capacitor value is
specified in the particular device’s Technical Data Sheet.
internal processor clock when the PLL is enabled and locked. When the PLL is
disabled, the output clock at CKOUT is derived from, and has the same
frequency and duty cycle as, EXTAL.
Note: If the PLL is enabled and the multiplication factor is less than or equal to
4, then CKOUT is synchronized to EXTAL.
This input pin defines the polarity of the CKOUT signal. Strapping CKP through
a resistor to GND will make the CKOUT polarity the same as the EXTAL
polarity. Strapping CKP through a resistor to VCC will make the CKOUT polarity
the inverse of the EXTAL polarity. The CKOUT clock polarity is internally
latched at the end of the hardware reset, so that any changes of the CKP pin
logic state after deassertion of RESET will not affect the CKOUT clock polarity.
During the assertion of hardware reset, the value at the PINIT input pin is
written into the PEN bit of the PLL control register. After hardware reset is
deasserted, the PINIT pin is ignored.
PLOCK when the PLL is enabled and has locked on the proper phase and
frequency of EXTAL. The PLOCK output is deasserted by the chip if the PLL is
enabled and has not locked on the proper phase and frequency. PLOCK is
asserted if the PLL is disabled. PLOCK is a reliable indicator of the PLL lock
state only after exiting the hardware reset state.
Freescale Semiconductor, Inc.
For More Information On This Product,
PLL CLOCK OSCILLATOR
Go to: www.freescale.com
PLL PINS
MOTOROLA