dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 182

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

shows how to program the MF0-MF11 bits. The VCO will oscillate at a frequency of
MF x F
chosen to ensure that the resulting VCO output frequency will lay in the range specified
in the device’s Technical Data Sheet. Any time a new value is written into the MF0-MF11
bits, the PLL will lose the lock condition. After a time delay, the PLL will relock. The
MF0-MF11 bits are set to a pre-determined value during hardware reset; the value is
implementation dependent and may be found in each DSP56K family member’s user
manual.
9.2.5.2 PCTL Division Factor Bits (DF0-DF3) - Bits 12-15
The Division Factor Bits DF0-DF3 define the divide factor (DF) of the low power divider.
These bits specify any power of two divide factor in the range from 2
9 - 6
ext
, where F
MF11
**
11
23
**
Reserved bits, read as zero, should be written with zero for future compatibility.
Table 9-1 Multiplication Factor Bits MF0-MF11
CKOS
MF10
ext
10
22
Figure 9-3 PLL Control Register (PCTL)
is the EXTAL clock frequency. The multiplication factor must be
Freescale Semiconductor, Inc.
CSRC
MF9
21
For More Information On This Product,
9
COD1
MF8
PLL CLOCK OSCILLATOR
8
20
MF11-MF0
Go to: www.freescale.com
PLL COMPONENTS
COD0
$FFE
$FFF
$000
$001
$002
MF7
7
19
MF6
PEN
6
18
PSTP
MF5
Multiplication
17
5
Factor MF
4095
4096
XTLD
MF4
1
2
3
16
4
MF3
DF3
3
15
MF2
DF2
2
14
MF1
DF1
1
13
0
MF0
DF0
to 2
0
12
15
MOTOROLA
. Table 9-2