dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 562

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
INSTRUCTION TIMING
cycles that may be required over and above those needed for the basic MACR instruc-
tion due to the parallel move portion of the instruction.
2. Evaluate the “mv’’ term using Table A-7.
The parallel move portion of the MACR instruction consists of an XY memory move.
According to Table A-7, the parallel move portion of the instruction will require mv=0
additional instruction program words and mv=(ea+axy) additional oscillator clock cycles.
The term “ea” represents the number of additional (if any) oscillator clock cycles that are
required for the effective addressing move specified in the parallel move portion of the
instruction. The term “axy” represents the number of additional (if any) oscillator clock
cycles that are required to access an XY memory operand.
3. Evaluate the “ea’’ term using Table A-13.
The parallel move portion of the MACR instruction consists of an XY memory move
which uses both address register banks (R0–R3 and R4–R7) in generating the effective
addresses of the XY memory operands. Thus, the two effective address operations
occur in parallel, and the larger of the two “ea’’ terms should be used. The X memory
move operation uses the “postdecrement by 1” effective addressing mode. According to
Table A-13, this operation will require ea=0 additional oscillator clock cycles. The Y
memory move operation uses the “postincrement by 1” effective addressing mode.
According to Table A-13, this operation will also require ea=0 additional oscillator clock
cycles. Thus, using the maximum value of “ea’’, the effective addressing modes used in
the parallel move portion of the MACR instruction will require ea=0 additional oscillator
clock cycles.
4. Evaluate the “axy’’ term using Table A-14.
The parallel move portion of the MACR instruction consists of an XY memory move.
According to Table A-14, the term “axy’’ depends upon where the referenced X and Y
memory locations are located in the DSP56K memory space. External memory
accesses require additional oscillator clock cycles according to the number of wait states
programmed into the DSP56K bus control register (BCR). Thus, assuming that the 16-bit
bus control register contains the value $1135, external X memory accesses require wx=1
w ait state of additional oscillator clock cycle while external Y memory accesses require
wy=1 w ait state or additional oscillator clock cycle. For this example, the X memory refer-
ence is assumed to be an internal reference; the Y memory reference is assumed to be
an external reference. Thus, according to Table A-14, the XY memory reference in the
parallel move portion of the MACR instruction will require axy=wy=1 additional oscillator
clock cycle.
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INSTRUCTION SET DETAILS
MOTOROLA
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