dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 561

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

including the number of words per instruction, the addressing mode, whether the instruc-
tion fetch pipe is full or not, the number of external bus accesses, and the number of wait
states inserted in each external access. The symbols used reference subsequent tables
to complete the execution clock cycle count.
All tables are based on the following assumptions:
To help the user better understand and use the timing tables, the following three exam-
ples illustrate the tables’ “layered’’ nature. (Remember that it is faster and simpler to use
the DSP56K simulator to calculate instruction timing.)
Example 16: Arithmetic Instruction with Two Parallel Moves
Problem: Calculate the number of 24-bit instruction program words and the number of
oscillator clock cycles required for the instruction
where
Solution: To determine the number of instruction program words and the number of
oscillator clock cycles required for the given instruction, the user should perform the fol-
lowing operations:
1. Look up the number of instruction program words and the number of oscillator clock
According to Table A-6, the MACR instruction will require (1+mv) instruction program
words and will execute in (2+mv) oscillator clock cycles. The term “mv’’ represents the
additional (if any) instruction program words and the additional (if any) oscillator clock
MOTOROLA
cycles required for the opcode-operand portion of the instruction in Table A-6.
1. All instruction cycles are counted in oscillator clock cycles .
2. The instruction fetch pipeline is full .
3. There is no contention for instruction fetches. Thus, external program instruc-
4. There are no wait states for instruction fetches done sequentially (as for non-
tion fetches are assumed not to have to contend with external data memory
accesses.
change-of-flow instructions), but they are taken into account for change-of-flow
instructions which flush the pipeline such as JMP, Jcc, RTI, etc.
Operating Mode Register (OMR)
Bus Control Register (BCR)
R6 Address Register
R0 Address Register
MACR –X0,X0,A
Freescale Semiconductor, Inc.
For More Information On This Product,
INSTRUCTION SET DETAILS
INSTRUCTION TIMING
Go to: www.freescale.com
X1,X:(R6)–
= $02 (normal expanded memory map),
= $1135,
= $0052 (internal X memory), and
= $0523 (external Y memory).
Y0,Y:(R0)+
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