dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 348

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Operation:
Assembler Syntax:
Description:
Divide the destination operand D by the source operand S and store the result in the
destination accumulator D. The 48-bit dividend must be a positive fraction which has
been sign extended to 56-bits and is stored in the full 56-bit destination accumula-
tor D. The 24-bit divisor is a signed fraction and is stored in the source operand S.
Each DIV iteration calculates one quotient bit using a nonrestoring fractional division
algorithm (see description on the next page). After the execution of the first DIV instruc-
tion, the destination operand holds both the partial remainder and the formed quotient.
The partial remainder occupies the high-order portion of the destination accumulator D
and is a signed fraction. The formed quotient occupies the low-order portion of the desti-
nation accumulator D (A0 or B0) and is a positive fraction. One bit of the formed quotient
is shifted into the LS bit of the destination accumulator at the start of each DIV iteration.
The formed quotient is the true quotient if the true quotient is positive. If the true quotient
is negative, the formed quotient must be negated. Valid results are obtained only
when |D| < |S| and the operands are interpreted as fractions. Note that this condition
ensures that the magnitude of the quotient is less than one (i.e., is fractional) and pre-
cludes division by zero.
A - 82
DIV
where
then
else
If
D[55] S[23]=1,
55
55
denotes the logical exclusive OR operator
Freescale Semiconductor, Inc.
For More Information On This Product,
DIV
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
Destination Accumulator D
Destination Accumulator D
47
47
Go to: www.freescale.com
S,D
Divide Interation
23
23
0
0
C+S
C–S
MOTOROLA
D
DIV
D