dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 521

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dsp56000

Manufacturer Part Number
dsp56000
Description
24-bit Digital Signal Processor Family Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Notes: If A or B is specified as the destination operand, the following sequence of events
If the system stack register SSH is specified as a source operand, the system stack
pointer (SP) is postdecremented by 1 after SSH has been read.
Timing: 4 oscillator clock cycles
Memory: 1 program word
MOTOROLA
REP
1. The S bit is computed according to its definition (See Section A.5 CON-
2. The accumulator value is scaled according to the scaling mode bits S0
3. If the accumulator extension is in use, the output of the shifter is limited
4. The LS 16 bits of the resulting 24 bit value is loaded into the loop
takes place:
DITION CODE COMPUTATION)
and S1 in the status register (SR).
to the maximum positive or negative saturation constant, and the L bit is
set.
counter (LC). The original contents of A or B are not changed.
Freescale Semiconductor, Inc.
INSTRUCTION SET DESCRIPTIONS
For More Information On This Product,
INSTRUCTION SET DETAILS
Repeat Next Instruction
Go to: www.freescale.com
REP
A - 255

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