dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 134

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

SP and SSH/SSL register manipulation restrictions:
In addition to all the above restrictions concerning SP, SSH, and SSL, the following
instruction sequences are illegal:
Also, the instruction MOVEC SSH,SSH is illegal.
Rn, Nn, and Mn register restrictions:
Due to pipelining, if an address register Rn is the destination of a MOVE-type instruction
except MOVEP (MOVE, MOVEC, MOVEM, LUA, Tcc), the new contents will not be
available for use as an address pointer until the second following instruction cycle.
Likewise, if an offset register Nn or a modifier register Mn is the destination of a MOVE-
type instruction except MOVEP, the new contents will not be available for use in address
calculations until the second following instruction cycle.
However, if the processor is in the No Update addressing mode (where Mn and Nn are
ignored) and register Mn or Nn is the destination of a MOVE instruction, the next instruc-
tion may use the corresponding Rn register as an address pointer. Also, if the processor
is in the Postincrement by 1, Postdecrement by 1, or Predecrement by 1 addressing
mode (where Nn is ignored), a MOVE to Nn may be immediately followed by an instruc-
tion that uses Rn as an address pointer.
Fast interrupt routines:
SWI, STOP, and WAIT may not be used in a fast interrupt routine. (Fast interrupts are
described in Section 7.3.1.)
7.3
The exception processing state is associated with interrupts that can be generated by
conditions inside the DSP or from external sources. In digital signal processing, one of
7 - 10
1. BCHG/BCLR/BSET SP
2. MOVEC/MOVEM/MOVEP from SSH or SSL
1. MOVEC/MOVEM to SP
2. MOVEC/MOVEM/MOVEP from SSH or SSL
1. MOVEC/MOVEM to SP
2. JCLR/JSET/JSCLR/JSSET SSH or SSL
1. BCHG/BCLR/BSET SP
2. JCLR/JSET/JSCLR/JSSET SSH or SSL
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
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