dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 46

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

3.4
The Data ALU double precision multiply operation multiplies two 48-bit operands with a
96-bit result. The processor enters the dedicated Double Precision Multiply Mode when
the user sets bit 14 (DM) of the Status Register (bit 6 of the MR register). The mode is
disabled by clearing the DM bit. For information on the DM bit, see Section 5.4.2.13 -
Double Precision Multiply Mode (Bit 14).
While in the Double Precision Multiply Mode, only the double precision multiply algorithms
shown in Figure 3-11, Figure 3-12, and Figure 3-13 may be executed by the Data ALU;
any other Data ALU operation will give indeterminate results.
Figure 3-11 shows the full double precision multiply algorithm. To allow for pipeline
delay, the ANDI instruction should not be immediately followed by a Data ALU instruc-
tion. For example, the ORI instruction sets the DM mode bit, but, due to the instruction
execution pipeline, the Data ALU enters the Double Precision Multiply mode only after
3 - 16
DOUBLE PRECISION MULTIPLY MODE
ori
move
mpy
mac
mac
mac
move
andi
non-Data ALU operation
Figure 3-11 Full Double Precision Multiply Algorithm
#$40,mr
y0,x0,a
x1,y0,a
x0,y1,a
y1,x1,a
a,l:(r0)+
#$bf,mr
DP3_DP2_DP1_DP0 = MSP1_LSP1 x MSP2_LSP2
R0
R1
DOUBLE PRECISION MULTIPLY MODE
Freescale Semiconductor, Inc.
For More Information On This Product,
x:(r1)+,x0
x:(r1)+,x1
a0,x:(r0)+
DATA ARITHMETIC LOGIC UNIT
MSP1
LSP1
Go to: www.freescale.com
DP3
DP1
X:
CAUTION:
y:(r5)+,y0
y:(r5)+,y1
a0,y:(r0)
MSP2
LSP2
DP2
DP0
Y:
;enter mode
;load operands
;LSP*LSP
;shifted(a)+
; MSP*LSP
;a+LSP*MSP
;shifted(a)+
; MSP*MSP
;exit mode
;pipeline delay
R5
R0
a
a
a
a
MOTOROLA