dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 294

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Operation:
Description: Add the source operand S to two times the destination operand D and
store the result in the destination accumulator. The destination operand D is arithmeti-
cally shifted one bit to the left, and a zero is shifted into the LS bit of D prior to the addi-
tion operation. The carry bit is set correctly if the source operand does not overflow as a
result of the left shift operation. The overflow bit may be set as a result of either the shift-
ing or addition operation (or both). This instruction is useful for efficient divide and deci-
mation in time (DIT) FFT algorithms.
Example:
Explanation of Example: Prior to execution, the 56-bit accumulator contains the value
$00:000000:000123,
$00:005000:000000. The ADDL A,B instruction adds two times the value in the B accu-
mulator to the value in the A accumulator and stores the 56-bit result in the B accumula-
tor.
A - 28
ADDL
S+2 D D (parallel move)
ADDL A,B #$0,R0
A
B
:
:
$00:005000:000000
$00:000000:000123
Before Execution
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and
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Shift Left and Add Accumulators
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
the
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56-bit
;A+2 B B, set up addr. reg. R0
B
Assembler Syntax:
A
B
accumulator
ADDL S,D (parallel move)
$00:000000:000123
$00:00A000:000123
After Execution
contains
ADDL
MOTOROLA
the
value