dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 629

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

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; Real input FFT based on Glenn Bergland algorithm
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; Normal order input and normal order output.
; Since 56001 does not support Bergland addressing, extra instruction cycles are needed
; for converting Bergland order to normal order.It has been done in the last pass by
; looking at the bergtable.
; 'bergsincos' generates sin and cos table with size of points/4,COS in Y, SIN in X
; 'bergorder' generates table for address conversion, the size of twiddle factors is half
; of FFT output's
; 'rfft-56b' does FFT
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; Normal order input and normal order output.
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; Real input data are split into two parts, the first part is put in X, the second in Y.
; Real output data are in X, imaginary output data are in Y.
; The first real output is DC
; The first imaginary output is the Nyquist frequency.
; Note that only DC to Nyquist frequency range is calculated by this algorithm
; After twiddle factors and bergtable are generated, you may overwrite 'bergorder',
; 'norm2berg' by 'rfft-56b' for saving P memory.
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Performance
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; Real input data points
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MOTOROLA
Intermediate Passes -- W(n) < 1
A---\
B----\_|_/----B’= Im[ A + jC - (B - jD)W(k) ] = C+DWr-BWi=T2+C
C----/ | \----C’= Re[ A + jC - (B - jD)W(k) ] = A-(BWr+DWi)=A-T1
D---/
/---A’= Re[ A + jC + (B - jD)W(k) ] = A+BWr+DWi=A+T1
\---D’= Im[-A - jC - (B - jD)W(k) ] = -C+DWr-BWi=T2-C
64
128
256
512
move
mpy
mac
sub
addl
mpy
mac
sub
addl
move
move
endm
x:(r0)+,x1 y:(r4)-,y1
x1,y0,B x:(r3)+,r7
x0,y1,B x:(r3)+,r1
B,A
A,B
y1,y0,A B,x:(r7)
-x1,x0,A y:(r4)+n4,B
B,A
A,B A,y:(r1)
x:(r0)+,A B,y:(r7)
y:(r4)+,B
Freescale Semiconductor, Inc.
For More Information On This Product,
x:(r2)+,x0 y:(r6)+,y0
A,x:(r1)
BENCHMARK PROGRAMS
BENCHMARK PROGRAMS
Go to: www.freescale.com
Clock cycle
1686
3846
8656
19296
;x1=b, y1=d, r4 ptr back to c
;A=bWr,
;B=bWr+dWi=T1, get first index
;A=a-T1=c’, get second index
;B=a+T1=a’, PUT c’ to x:b
;B=dWr, B=c PUT a’
;A=dWi-bWr=T2, B=c, r4 ptr to next c
;A=T2-c=d’,x0=next Wi, y0=next Wr
;B=T2+c=b’, update r4, A=next a, PUT d’
;PUT b’, A=next a
;B=next c
B - 25