dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 138

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

ority levels, see the individual DSP56K family member’s User’s Manual.
7.3.2.1 Interrupt Priority Levels
The IPL for each on-chip peripheral device (HI, SSI, SCI) and for each external interrupt
source (IRQA, IRQB) can be programmed to one of the three maskable priority levels
(IPL 0, 1, or 2) under software control. IPLs are set by writing to the interrupt priority reg-
ister shown in Figure 7-2. This read/write register is located in program memory at
address $FFFF. It specifies the IPL for each of the interrupting devices including IRQA,
IRQB and each peripheral device. (For specific peripheral information, see the specific
DSP56K family member’s User’s Manual.) In addition, it specifies the trigger mode of the
external interrupt sources and is used to enable or disable the individual external inter-
rupts. The interrupt priority register is cleared on RESET or by the reset instruction.
Table 7-3 defines the IPL bits. Table 7-4 defines the external interrupt trigger mode bits.
7.3.2.2 Exception Priorities Within an IPL
If more than one interrupt is pending when an instruction is executed, the processor will
service the interrupt with the highest priority level first. When multiple interrupt requests
7 - 14
23
**
Bits 6 to 9 are reserved, read as zero and should be written with zero for future compatibility.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
Figure 7-2 Interrupt Priority Register (Addr X:$FFFF)
I1
0
0
1
1
Table 7-2 Status Register Interrupt Mask Bits
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I0
0
1
0
1
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10
**
Exceptions Permitted
9
*
PROCESSING STATES
IPL 0, 1, 2, 3
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IPL 1, 2, 3
IPL 2, 3
IPL 3
8
*
7
*
6
*
IBL2
5
Exceptions Masked
IBL1
4
RESERVED FOR PERIPHERAL IPL LEVELS
IPL 0, 1, 2
IPL 0, 1
IBL0
None
IPL 0
3
IAL2
2
RESERVED FOR EXPANSION
IAL1 IAL0
1
0
MOTOROLA
IRQA MODE
IRQB MODE