pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 158

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

an external second timer is possible which has to be provided on pin SEC/FSC.
Selecting the external second timer is done with GCR.SES. Refer also to register GPC1
for input/output selection.
5.3.6
For support of common T1 applications, clear channels can be specified through the
3-byte register bank CCB(1:3). In this mode the contents of selected transmit time slots
are not overwritten by internally or externally sourced bit-robbing and zero code
suppression (B7 stuffing) information.
5.3.7
The FALC
00001) and loop-down (deactivate, 001) pattern according to ANSI T1.403 with bit error
rates as high as 10
Replacing the in-band loop codes with transmit data is done by FMR5.XLD/XLU.
The FALC
loop-up and -down pattern (LCR1.LLBP = 1). The loop-up and loop-down pattern is
individually programmable from 2 to 8 bits in length (LCR1.LAC1/0 and LCR1.LDC1/0).
Programming of loop codes is done in registers LCR2 and LCR3.
Status and interrupt status bits inform the user whether loop-up or loop-down code was
detected.
5.3.8
The transparent modes are useful for loop-backs or for routing data unchanged through
the FALC
In receive direction, transparency for ternary or dual-/single-rail unipolar data is always
achieved if the receiver is in the synchronous state. All bits in F-bit position of the
incoming multiframe are forwarded to RDO and inserted in the FS/DL time slot or in the
F-bit position. In asynchronous state the received data is switched through transparently
if bit FMR2.DAIS is set. Setting of bit LOOP.RTM disconnects control of the elastic buffer
from the receiver. The elastic buffer is now in a “free running” mode without any
possibility to update the time slot assignment to a new frame position in case of
resynchronization of the receiver. Together with FMR2.DAIS this function is used to
realize undisturbed transparent reception.
Setting bit FMR4.TM switches the FALC
In transmit direction bit 8 of the FS/DL time slot from the system highway (XDI) is inserted
in the F-bit position of the outgoing frame. For complete transparency the internal
signaling controller, idle code generation, AIS alarm generation, single channel and
payload loop-back has to be disabled and cleared channels have to be defined by
registers CCB1… 3.
User’s Manual
Hardware Description
®
®
56.
®
Clear Channel Capability
In-Band Loop Generation and Detection
Transparent Mode
56 generates and detects a framed or unframed in-band loop-up (activate,
56 also offers the ability generating and detecting of a flexible in-band
-2
. Framed or unframed in-band loop code is selected by LCR1.FLLB.
®
56 in transmit transparent mode:
158
Functional Description T1/J1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56