pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 70

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

•
If a loss-of-signal condition is detected, the data stream can optionally be cleared
automatically to avoid bit errors before LOS is indicated. The selection is done by
LIM1.CLOS = 1.
4.1.10
The receive jitter attenuator is placed in the receive path. The working clock is an
internally generated high frequency clock based on the clock provided on pin MCLK. The
jitter attenuator meets the requirements of ITU-T I.431, G. 736 to 739, G.823 and ETSI
TBR12/13.
The internal PLL circuitry DCO-R generates a "jitter-free" output clock which is directly
dependent on the phase difference of the incoming clock and the jitter attenuated
clock.The receive jitter attenuator can be synchronized either on the extracted receive
clock RCLK or on a 2.048-MHz/8-kHz clock provided on pin SYNC (8 kHz in master
mode only). The received data is written into the receive elastic buffer with RCLK and
are read out with the de-jittered clock sourced by DCO-R. The jitter attenuated clock can
be output on pins RCLK, CLK1 or SCLKR. Optionally an 8-kHz clock is provided on pin
SEC/FSC.
The DCO-R circuitry attenuates the incoming jittered clock starting at 2-Hz jitter
frequency with 20 dB per decade fall-off. Wander with a jitter frequency below 2 Hz is
bypassed unattenuatedly. The intrinsic jitter in the absence of any input jitter is < 0.02 UI.
For some applications it might be useful to start jitter attenuation at lower frequencies.
Therefore the corner frequency is switchable by the factor of ten down to 0.2 Hz
(LIM2.SCF).
The DCO-R circuitry is automatically centered to the nominal bit rate if the reference
clock on pin SYNC/RCLK is missed for 2, 3 or 4 of the 2.048-MHz clock periods. This
center function of DCO-R can be disabled (CMR2.DCF = 1) in order to accept a gapped
reference clock. In analog line interface mode RCLK is always running. Only in digital
line interface mode with single-rail data a gapped clock can occur.
The receive jitter attenuator works in two different modes:
User’s Manual
Hardware Description
control bits LIM1.RIL(2:0) (see
by an 8-bit register (PCD). The contents of the PCD register is multiplied by 16, which
results in the number of pulse periods, i.e. the time which has to suspend until the
alarm has to be detected. The programmable range is 16 to 4096 pulse periods.
ETS300233 requires detection intervals of at least 1 ms. This time period results
always in a LFA (Loss of Frame Alignment) before a LOS is detected.
Recovery:
In general the recovery procedure starts after detecting a logical one (digital receive
interface) or a pulse (analog receive interface) with an amplitude more than Q dB
(defined by LIM1.RIL(2:0)) of the nominal pulse. The value in the 8-bit register PCR
defines the number of pulses (1 to 255) to clear the LOS alarm.
Receive Jitter Attenuator (E1)
Chapter 11.3
70
on page 466). The number N can be set
Functional Description E1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
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