pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 95

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

4.3.2.4
In slave mode (LIM0.MAS = 0) the DCO-R synchronizes to the recovered route clock. In
case of loss-of-signal (LOS) the DCO-R switches to Master mode automatically. If bit
CMR1.DCS is set, automatic switching from RCLK to SYNC is disabled.
4.3.2.5
Updating of the received signaling information is controlled by the freeze signaling
status. The freeze signaling status is automatically activated if a loss-of-signal or a loss
of CAS multiframe alignment or a receive slip occurs. The internal signaling buffer
RS(16:1) is frozen. Optionally automatic freeze signaling is disabled by setting bit
SIC3.DAF.
4.3.3
The FALC
record code violations, framing bit errors, CRC4-bit errors and CRC4 error events which
are flagged in the different S
in asynchronous state or the Change Of Frame Alignment (COFA). Counting of the
multiframes in the asynchronous state and the COFA parameter is done in a 6/2 bit
counter and is shared with CEC3L/H. Each of the error counters is buffered. Buffer
updating is done in two modes:
•
•
In the one-second mode an internal/external one-second timer updates these buffers
and resets the counter to accumulate the error events in the next one-second period.
The error counter cannot overflow. Error events occurring during an error counter reset
are not lost.
4.3.4
The FALC
alarms or error events in the received data:
framing errors, CRC errors, code violations, loss of frame alignment, loss-of-signal,
alarm indication signal, E-bit error, receive and transmit slips.
With a programmable interrupt mask register ESM all these alarms or error events can
generate an errored second interrupt (ISR3.ES) if enabled.
4.3.5
Additionally, a one-second timer interrupt can be generated internally to indicate that the
enabled alarm status bits or the error counters have to be checked. The one-second
timer signal is output on port SEC/FSC (GPC1.CSFP1/0). Optionally synchronization to
User’s Manual
Hardware Description
One-second accumulation
On demand by handshake with writing to the DEC register
®
®
Automatic Clock Source Switching
Automatic Freeze Signaling
Error Counters
Errored Second
One-Second Timer
56 offers six error counters where each of them has a length of 16 bit. They
56 supports the error performance monitoring by detecting the following
a
6-bit combinations or the number of received multiframes
95
Functional Description E1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56