pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 40

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 4
Pin or
Ball No.
67 (D6)
68 (A6)
69 (B5)
70 (D5)
User’s Manual
Hardware Description
Name
RPA
RPB
RBC
RPD
Pin Definitions - System Interface (cont’d)
Pin
Type
O
O
Buffer
Type
Function
Receive Frame Marker (RFM)
PC(1:4).RPC(3:0) = 0010
Two different modes are provided for this
signal, selected by CMR2.IRSP.
0
1
Receive Multiframe Begin (RMFB)
PC(1:4).RPC(3:0) = 0010
In E1 mode RMFB marks the beginning of
every received multiframe (RDO). Optionally
the time slot 16 CAS multiframe begin can be
marked (SIC3.CASMF). Active high for one
2.048 MHz period.
In T1/J1 mode the function depends on bit
XC0.MFBS:
0
1
40
B
B
B
B
IRSP_0, The receive frame marker can
be active high for a 2.048 MHz (E1) or
1.544 MHz (T1/J1) period during any
bit position of the current frame. It is
clocked off with the rising or falling
edge of SCLKR or RCLK, depending
on SIC3.RESR. Offset programming is
done by using registers RC(1:0).
IRSP_1, Frame synchronization pulse
generated by the DCO-R circuitry
internally. Together with registers
RC(1:0) the frame begin on the receive
system interface is defined. This frame
synchronization pulse is active low for a
2.048 MHz (E1) or 1.544 MHz (T1/J1)
period.
MFBS_0, RMFB marks the beginning
of every received multiframe (RDO).
MFBS_1, RMFB marks the beginning
of every received superframe.
Additional pulses are provided every 12
frames when using ESF/F24 or F72
format.
B
B
External Signals
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56