pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 172

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 45
System Data Rate
1.544/2.048 Mbit/s
3.088/4.096 Mbit/s
6.176/8.192 Mbit/s
12.352/16.384 Mbit/s
× = valid, - = invalid
Generally the data or marker on the system interface are clocked off or latched on the
rising or falling edge (SIC3.RESR/X) of the SCLKR/X clock. Some clocking rates allow
transmission of time slots in different channel phases. Each channel phase which shall
be active on ports RDO, XDI, RP(A:D) and XP(A:D) is programmable by bit
SIC2.SICS(2:0), the remaining channel phases are cleared or ignored.
The signals on pin SYPR in combination with the assigned time slot offset in register RC0
and RC1 define the beginning of a frame on the receive system highway. The signal on
pin SYPX or XMFS together with the assigned time slot offset in register XC0 and XC1
define the beginning of a frame on the transmit system highway.
Adjusting the frame begin (time slot 0, bit 0) relative to SYPR/X or XMFS is possible in
the range of 0 to 125 µs. The minimum shift of varying the time slot 0 begin can be
programmed between 1 bit and 1/8 bit depending of the system clocking and data rate,
e.g. with a clocking/data rate of 2.048 MHz shifting is done bit by bit, while running the
FALC
A receive frame marker RFM can be activated during any bit position of the entire frame.
Programming is done with registers RC1/0. The pin function RFM is selected by
PC(4:1).RPC(2:0) = 001. The RFM selection disables the internal time slot assigner, no
offset programming is performed. The receive frame marker is active high for one
1.544/2.048 MHz cycle or one system clock cycle (see GPC1.SRFM) and is clocked off
with the rising or falling edge of the clock which is in/output on port SCLKR (see
SIC3.RESX/R).
User’s Manual
Hardware Description
®
56 with 16.384 MHz and 2.048 Mbit/s data rate it is done by 1/8 bit.
System Clocking and Data Rates (T1/J1)
Clock Rate
1.544/2.048
MHz
×
-
-
-
Clock Rate
3.088/4.096
MHz
×
×
-
-
172
Functional Description T1/J1
Clock Rate
6.176/8.192
MHz
×
×
×
-
DS1.1, 2003-10-23
PEF 2256 H/E
Clock Rate
12.352/16.38
4 MHz
×
×
×
×
FALC
®
56