pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 450

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Interrupt Status Register 3 (Read)
All bits are reset when ISR3 is read.
If bit GCR.VIS is set, interrupt statuses in ISR3 are flagged although they are masked by
register IMR3. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
ES
SEC
LLBSC
User’s Manual
Hardware Description
Errored Second
This bit is set if at least one enabled interrupt source by ESM is set
during the time interval of one second. Interrupt sources of ESM
register:
LFA = Loss of frame alignment detected
FER = Framing error received
CER = CRC error received
AIS
LOS = Loss-of-signal (red alarm)
CVE = Code violation detected
SLIP = Transmit slip or receive slip positive/negative detected
Second Timer
The internal one-second timer has expired. The timer is derived from
clock RCLK.
Line Loop-Back Status Change/PRBS Status Change
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
LCR1.EPRM = 0: This bit is set, if the LLB activate signal or the LLB
deactivate signal is detected over a period of 33.16 ms with a bit error
rate less than 10
The LLBSC bit is also set, if the current detection status is left, i.e., if
the bit error rate exceeds 10
The actual detection status can be read from the FRS1.LLBAD and
FRS1.LLBDD, respectively.
PRBS Status Change
LCR1.EPRM = 1: With any change of state of the PRBS synchronizer
this bit is set. The current status of the PRBS synchronizer is
indicated in FRS1.LLBAD.
= Alarm indication signal (blue alarm)
-2
.
450
-2
.
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FALC
®
56