pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 161

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

®
FALC
56
PEF 2256 H/E
Functional Description T1/J1
5.4.3
Transmit Jitter Attenuator (T1/J1)
The transmit jitter attenuator DCO-X circuitry generates a "jitter-free" transmit clock and
meets the following requirements: PUB 62411, PUB 43802, TR-TSY 009,TR-TSY 253,
TR-TSY 499 and ITU-T I.431 and G.703. The DCO-X circuitry works internally with the
same high frequency clock as the receive jitter attenuator. It synchronizes either to the
working clock of the transmit backplane interface or the clock provided on pin TCLK or
the receive clock RCLK (remote loop/loop-timed). The DCO-X attenuates the incoming
jitter starting at 6 Hz with 20 dB per decade fall-off. With the jitter attenuated clock, which
is directly depending on the phase difference of the incoming clock and the jitter
attenuated clock, data is read from the transmit elastic buffer (2 frames) or from the JATT
buffer (2 frames, remote loop). Wander with a jitter frequency below 6 Hz is passed
transparently.
The DCO-X accepts gapped clocks which are used in ATM or SDH/SONET applications.
The jitter attenuated clock is output on pin XCLK or optionally on pin CLK2.
In case of missing clock on pin SCLKX the DCO-X centers automatically, if selected by
bit CMR2.DCOXC = 1.
The transmit jitter attenuator can be disabled. In that case data is read from the transmit
elastic buffer with the clock sourced on pin TCLK (1.544 or 6.176 MHz). Synchronization
between SCLKX and TCLK has to be done externally.
In the loop-timed clock configuration (LIM2.ELT) the DCO-X circuitry generates a
transmit clock which is frequency synchronized on RCLK. In this configuration the
transmit elastic buffer has to be enabled.
User’s Manual
161
DS1.1, 2003-10-23
Hardware Description