pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 447

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Interrupt Status Register 1 (Read)
All bits are reset when ISR1 is read.
If bit GCR.VIS is set, interrupt statuses in ISR1 are flagged although they are masked by
register IMR1. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
CASE
RDO
ALLS
XDU
User’s Manual
Hardware Description
Transmit CAS Register Empty
In ESF format this bit is set with the beginning of a transmitted
multiframe related to the internal transmitter timing. In F12 and F72
format this interrupt occurs every 24 frames to inform the user that
new bit robbing data may be written to the XS(12:1) registers. This
interrupt is generated only if the serial signaling access on the system
highway is not enabled.
Receive Data Overflow - HDLC Channel 1
This interrupt status indicates that the CPU did not respond fast
enough to an RPF or RME interrupt and that data in RFIFO has been
lost. Even when this interrupt status is generated, the frame continues
to be received when space in the RFIFO is available again.
Note: Whereas the bit RSIS.RDO in the frame status byte indicates
All Sent - HDLC Channel 1
This bit is set if the last bit of the current frame has been sent
completely and XFIFO is empty. This bit is valid in HDLC mode only.
Transmit Data Underrun - HDLC Channel 1
Transmitted frame was terminated with an abort sequence because
no data was available for transmission in XFIFO and no XME was
issued.
Note: Transmitter and XFIFO are reset and deactivated if this
whether an overflow occurred when receiving the frame
currently accessed in the RFIFO, the ISR1.RDO interrupt status
is generated as soon as an overflow occurs and does not
necessarily pertain to the frame currently accessed by the
processor.
condition occurs. They are reactivated not before this interrupt
status register has been read. Thus, XDU should not be
masked by register IMR1.
447
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FALC
®
56