pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 339

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Receive Signaling Status Register 2 (Read)
Value after reset: 00
RSIS2
RSIS2 relates to the last received HDLC channel 2 frame; it is copied into RFIFO2 when
end-of-frame is recognized (last byte of each stored frame).
VFR2
RDO2
CRC162
RAB2
User’s Manual
Hardware Description
VFR2
Valid Frame - HDLC Channel 2
Determines whether a valid frame has been received.
1 =
0 =
An invalid frame is either
– a frame which is not an integer number of 8 bits (n× 8 bits) in length
– a frame which is too short taking into account the operation mode
Note:Shorter frames are not reported.
Receive Data Overflow - HDLC Channel 2
A data overflow has occurred during reception of the frame.
Additionally, an interrupt can be generated
(refer to ISR4.RDO2/IMR4.RDO2).
CRC16 Compare/Check - HDLC Channel 2
0 =
1 =
Receive Message Aborted - HDLC Channel 2
This bit is set, if more than 5 contiguous 1-bits are detected.
RDO2
H
(e.g. 25 bits), or
selected via MODE2 (MDS2(2:0)) and the selection of receive CRC
ON/OFF (CCR3.RCRC2) as follows:
• MDS2(2:0)=011 (16 bit Address),
• MDS2(2:0)=010 (8 bit Address),
RCRC2=0: 4 bytes; RCRC2=1: 3 or 4 bytes
RCRC2=0: 3 bytes; RCRC2=1: 2 or 3 bytes
CRC check failed; received frame contains errors.
CRC check o.k.; received frame is error-free.
Valid
Invalid
CRC162
RAB2
339
HA12
HA02
DS1.1, 2003-10-23
PEF 2256 H/E
LA2
E1 Registers
FALC
(AA)
®
56