pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 432
pef2256e
Manufacturer Part Number
pef2256e
Description
E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF2256E.pdf
(518 pages)
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Framer Receive Status Register 2 (Read)
ESC(2:0)
Table 73
Tested Alarms ESC(2:0) =
LFA
LMFA
RRA (bit2 = 0)
RRA (S-bit frame 12)
RRA (DL-pattern)
LOS
EBC
EBC
AIS
FEC
CVC
CEC (only ESF)
RSP
RSN
XSP
XSN
BEC
COEC
1)
2)
User’s Manual
Hardware Description
only active during FMR0.SIM = 1
FEC is counting +2 while EBC is counting +1 if the framer is in synchronous state; if asynchronous in state 2
but synchronous in state 6, counters are incremented during state 6
1)
1)
2)
2)
2)
1)
(F12,F72)
(only ESF)
Alarm Simulation States
Error Simulation Counter
This three-bit counter is incremented by setting bit FMR0.SIM. The
state of the counter determines the function to be tested.
For complete checking of the alarm indications, eight simulation steps
are necessary (FRS2.ESC = 0 after a complete simulation).
0
432
1
×
×
×
×
×
×
×
×
×
2
×
×
×
×
×
×
×
×
×
×
×
×
3
4
5
×
×
×
×
×
×
×
×
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
6
×
×
×
(× )
(× )
×
(× )
×
×
FALC
7
®
56
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