pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 87

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

For transmit direction, contents of time slot 0 are additionally determined by the selected
transparent mode.
Table 20
enabled by
–
XSP.TT0
TSWM.TSIF
TSWM.TSIS
TSWM.TRA
TSWM.TSA(8:4)
1)
2)
3)
4)
The CRC procedure is automatically invoked when the multiframe structure is enabled.
CRC errors in the received data stream are counted by the 16-bit CRC Error Counter
CEC (one error per submultiframe, maximum).
Additionally a CRC4 error interrupt status ISR0.CRC4 is generated if enabled by
IMR0.CRC4.
All CRC bits of one outgoing submultiframe are automatically inverted in case a CRC
error is flagged for the previous received submultiframe. This function is enabled by bit
RC0.CRCI. Setting of bit RC0.XCRCI inverts the CRC bits before transmission to the
distant end. The function of RC0.XCRCI and RC0.CRCI are logically ored.
4.2.3.1
Multiframe alignment is assumed to have been lost if doubleframe alignment has been
lost (flagged on status bit FRS0.LFA). The rising edge of this bit causes an interrupt.
The multiframe resynchronization procedure starts when Doubleframe alignment has
been regained which is indicated by an interrupt status bit ISR2.FAR. For Doubleframe
synchronization refer to section Doubleframe Format. It is also be invoked by the user
by setting
•
•
The CRC checking mechanism is enabled after the first correct multiframe pattern has
been found. However, CRC errors are not counted in asynchronous state.
User’s Manual
Hardware Description
pin XDI or XSIG or XFIFO buffer (signaling controller)
Automatic transmission of the A-bit is selectable
The S
Additionally, automatic transmission of submultiframe error indication is selectable
Bit FMR0.FRS for complete doubleframe and multiframe resynchronization
Bit FMR1.MFCS for multiframe resynchronization only.
a
-bit register XSA(8:4) can be used optionally
Synchronization Procedure
Transmit Transparent Mode (CRC Multiframe E1)
Transmit Transparent Source for
Framing +
CRC
(int. gen.)
via pin XDI
via pin XDI
via pin XDI
(int. gen.)
(int. gen.)
1)
A-Bit
XSW.XRA
via pin XDI
XSW.XRA
XSW.XRA
via pin XDI
XSW.XRA
87
2)
1)
1)
1)
S
XSW.XY0 … 4
via pin XDI
XSW.XY0 … 4
XSW.XY0 … 4
XSW.XY0 … 4
via pin XDI
a
-Bits
Functional Description E1
3)
2)
2)
2)
E-Bits
XSP.XS13/XS15
via pin XDI
(int. generated)
via pin XDI
XSP.XS13/XS15
XSP.XS13/XS15
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56
4)
3)
3)